Awg7102 manual

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Page 49 Ch 2 1. Page 50 1. Verify that the frequency counter reading falls within the range of 9. Disconnect the test setup. Set the digital multimeter to the VDC mode.

Page Table Analog Offset Accuracy Page Table Analog Amplitude Accuracy 3 on page Repeat steps 7 through 16 for each amplitude setting in Table Page Table Analog Harmonic Distortion Page 70 Page Marker Output Delay Accuracy 4. Page 73 Repeat steps 5 through 10 for each row in Table This completes the AWG performance verification.

This manual is also suitable for: Awg Awg Awg Awg Print page 1 Print document 76 pages. Rename the bookmark. Delete bookmark? Cancel Delete.

Delete from my manuals? Sign In OR. Don't have an account? Sign up! Restore password. Upload manual. Upload from disk. Upload from URL. A low noise reference is used to generate reference voltages for all the scope stages. Buffered and scaled replicas of the reference voltages are provided for the buffer stages and individually for each scope channel to minimize crosstalk.

A dual channel DAC generates the offset voltages, to be added over the input signal, for vertical position. Buffers are used to provide low impedance. IC2 Fig. The common mode voltage range is:. Simulation results are shown below. The Phase jitter using a brick wall filter The differential inputs are driven via a low-pass filter comprised of C together with R10 through R13, in the buffer stage. The differential clock is AC-coupled and the line is impedance matched.

The clock is internally divided by two for operating at a constant MHz sampling rate. An external reference voltage is used, buffered by IC To minimize the number of used FPGA pins; a multiplexed mode is used, to combine the two channels on a single data bus. To cover component value tolerances and to allow software calibration, only the ranges below are specified. With the bit ADC , the absolute resolution of the scope is:. Combining these with the gain equations, the overall linear scope operation range is shown Figs.

Each equation is represented by a closed polygon. Each figure is shown at the full range and at a detailed range. Separate figures are shown for low-gain and for high-gain. Only the differential input voltage is shown on the scope screen.

The common mode voltage information is removed by the differential structure of the Analog Discovery 2 scope. A signal overpassing the linear range will be distorted on the scope screen, i. In the diagrams below, a signal outside the linear range will be clamped to the closest point in the linear range. The clamping point is not necessarily at the scope screen top or bottom edge, as explained below. The dashed rectangles represent the display area on the scope screen.

Any intermediate vertical position is possible, moving the displayable area virtual dashed rectangle to any intermediate position. A signal crossing the long side of the dashed rectangle exceeds the displayable input voltage range causing the ADC to saturate either at zero or at Full Scale.

This is represented on the scope screen with dashed line warning to the user. A signal keeping within the dashed rectangle but crossing any solid line overrides electrical limits of intermediate circuits in the signal path see the legend of the figures. This results in distorting the signal without saturating the ADC.

The software has no information about this situation and cannot warn the user with specific signal representation. For low gain Fig. For high gain Fig. Additionally, the differential input signal combined with the equivalent offset voltage — vertical position is visible only within the range:.

Figure 13 shows an example of a signal distorted due to a common mode input voltage that is too large. The grey line is the reference, not distorted, signal. The differential input voltage is a 4Vpp triangle on top of a -5V DC component. The common mode input voltage is 10V. The vertical position of the scope is set to 5V and high gain is selected. The yellow line shows an identical signal, except the common mode input voltage is 15V. Figure 14 shows a typical spectral characteristic of the scope.

The signal swept from Hz to 30 MHz. The Network Analyzer was used, the WaveGen was set to External, the Gain was set at x10 high-gain for the upper figure, and x0. The 0. The standard -3dB bandwidth definition is derived from filter theory. At cutout frequency, the scope attenuates the spectral components by 0. The bandwidth with a specified flatness is useful to better define the scope spectral performances. The Analog Discovery 2 exhibits 10 MHz 0. As shown above, the measurements in Fig.

This is the optimal setup that allows maximal Analog Discovery spectral performance. The wire kit included with the Analog Discovery 2 is a cheap, easy-to-use probing solution.

However, the wire kit reduces the bandwidth of the scope and is susceptible to inducing noise and crosstalk from adjacent circuits. The main features are:. The single ended MHz clock is provided by the clock generator. The ADG 2. The ADG features:. As shown in Fig. A divided version is provided to the DAC :. IC 15 in Fig.

Important AD features:. IC16 in Fig. AD features:. Low-gain is used to generate low amplitude signals with improved accuracy. A stereo audio output combines the two AWG channels Fig. AD was used for its features:.

The second term is the common mode DC component, removed by AC coupling. Figure 21 shows the typical spectral characteristic of the AWG. For the second experiment down , the AWG was connected to the scope inputs via the Analog Discovery wire kit.

The Analog Discovery 2 Scope hardware was considered a reference for the experiments above because it has preferred spectral characteristics to the AWG. The Network Analyzer virtual instrument in WaveForms is used to perform synchronized signal synthesis and acquisition. It takes control of channel 1 of AWG and of both scope channels. Sinus amplitude is set to 1V. The characteristic is built in steps.

The analog circuitry described in previous chapters includes passive and active electronic components. The datasheet specs show parameters resistance, capacitance, offsets, bias currents, etc.

The equations in previous chapters consider typical values. To minimize these effects, the design uses:. A software calibration is performed on each device as a part of the manufacturing test. AWG signals are passed to a reference instrument and reference signals are connected to the Scope inputs. A set of measurements is used to identify all the DC errors Gain, Offset of each analog stage. Correction Calibration parameters are computed and stored in the Calibration Memory, on the Analog Discovery 2 device, as Factory Calibration.

The WaveForms software allows the user performing an in-house calibration and overwrite the Calibration Data. Returning to Factory Calibration is always possible. The WaveForms Software reads the calibration parameters from the connected Analog Discovery 2 and uses them to correct both generated and acquired signals.

J3 is the Analog Discovery 2 user signal connector. PTC thermistors provide thermal protection in case of shortcuts. For output pins, the PTCs and the load impedance limit the bandwidth and power. Inputs are 5V tolerant. This block includes all power monitoring and control circuitry, internal power supplies, and user power supplies.

The external power input is protected against reverse voltage; Q4 turns OFF if a floating power supply with negative polarity on central pin of J4 is used. However, the device is not protected for a very unlikely use case:.

ADCMP is a window comparator with the following features:. Running instruments are not affected, except User Supplies get more available power. However, removing the external power supply during External mode is not seamless. The FPGA gets unpowered and loses configuration data.

All the instruments can then be run, in the USB mode. A hot swap retry is initiated after:. Similarly, IC26 in Racing or External modes , limits the current consumed from the external power supply to:. The Analog Discovery 2 user pins are overvoltage protected. If the back-powered energy is higher than the used energy, the bi-directional power supply recovers the difference and delivers it to the previous node in the power chain.

D28 in Fig. ADP main features:. IC27 in Fig. ADM was selected for its main features:. IC27 limits the current consumed by both user power supplies together.